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The makeup of the semiconductor industry is changing and growing again. This time around, it’s a variety of companies, including tech giants Apple, Amazon, Facebook, Microsoft, and Tesla, which were previously not known to be in the chip development business, behind the change. They hire experienced engineers to design higher performance and energy efficient computer chips for all kinds of applications, from networking and cloud to autonomous driving. Along the way, they tear up the pages of the traditional semiconductor manual and put together their own individual semiconductor design guides. The result is tailor-made chips rather than using a generic chip to meet their needs.
These systems companies also secretly and, perhaps, secretly keep their projects secret and build an intellectual property (IP) portfolio that they wish to protect and differentiate themselves from their competitors. They want control and the ability to customize their own IP. They are also looking for supplier partners who are willing to go the extra mile to ensure their chips are suitable for their specific applications. Obviously, these companies want strategic, multi-year deals with partners who won’t share their differentiation and will pay more than a typical proposition, accomplished if the business managers are creative.
Yes, the traditional stages of the system design process as we know them are changing. Perhaps the first to notice the trend is the starting point of electronics – computer aided design (CAD), now popularly known as the electronic design automation (EDA) community or electronic design community. electronic systems (ESD). This scenario is an evolution for a community serving the semiconductor industry with design tools since the 1980s.
It all started with support for custom silicon designs, then moved on to semi-custom design and ASICs and the rise of factory-less semiconductors. A more recent trend fully embraced about 15 years ago, IP blocks are built into designs, developed in-house or licensed from an IP vendor, such as Arm, and often function as the differentiator to do not share the business. IP has changed the way chips are designed, from handcrafting every function at the transistor level to using building blocks, ushering in the era of the system on a chip (SoC). Once again, the tools of this community have been developed to meet the need.
Today, the personalized approach has moved to design and verification flows to serve as differentiators. And why not? Design and verification flows are a necessary part of chip design and include a combination of point tools that are generic by design to appeal to a large community of engineering groups. All customization is therefore done internally.
Differentiation or not, all semiconductor companies rely on point-in-time tools to ensure their design and verification workflows meet industry standards. In many cases, new systems houses want tools customized at higher levels of abstraction and not widely shared with their competition. In the past, if the tool vendor made the change, the change to a customer’s name would become a feature in the next release of the software tool within six months.
The best analogy for the change sweeping the design tool vendor community may be the aftermarket car dealership customizing a car that ships with standard features. The aftermarket will complement it with the features the owner wants tailored to their explicit needs.
In the semiconductor industry, a design tools company could be the aftermarket auto dealer meeting differentiation and standards compliance by offering a software development platform implemented in design workflows. and verification. The platform could allow a company to customize their semiconductor design workflow for their specific applications without worrying about the customization being shared externally. This is an advantage for any semiconductor company that is wary of competitors who identify and replicate their design flow or implementation techniques.
The scenario plays out in large and small chip development companies. One example is a spin-off start-up from one of the new systems design companies. It develops chip solutions to accelerate server performance. He wanted to optimize his design for performance and did so by refining the design to a higher level of abstraction than the gate or register transfer level.
Design tool companies willing to partner, customize, and / or optimize their software platform to specific needs deliver high value. Smaller, more agile companies may offer a more personalized approach, while larger, more established companies will catch up as the trend occurs across the semiconductor design ecosystem.
For now, tech giants and system design companies are sticking to the chip design and verification part of the supply chain and not investing in manufacturing and foundries. This is no wonder at a cost that could exceed $ 10 billion and a time investment of several years.
Ultimately, personalization is market segmentation. Design tools modify but do not change the tool flow. They enhance it with a special insert for New Intellectual Property, a new feature that improves or optimizes a design to create a unique end product without changing or altering anything downstream. Customizing at the highest levels of abstraction also has no impact on production, other than better and more efficient power or performance design.
As this trend continues in the semiconductor industry and disrupts the way chips are designed and verified, companies large and small are turning to their design tool vendors, exploring new business models, partnerships and differentiators to maintain their competitive advantage.
– Rick Carlson is Vice President of Global Sales for Verification Design Automation. A veteran of the Electronic Design Automation (EDA) industry, he joined Verific from AccelChip where he held a similar role. Prior to AccelChip, Carlson served as Vice President of Sales for Averant, Synplicity (acquired by Synopsys), Escalade (acquired by Siemens) and EDA Systems. He co-founded the EDA Consortium (now the ESD Alliance, a SEMI technology community) in 1987. He holds a Bachelor of Science in Mathematics from the Illinois Institute of Technology (IIT) in Chicago.